Capsules for VHDL and Verilog Tools
Capsules for VHDL Tools
A useful tool for VHDL capsules is vhdlpp
. This is based on a
proprietary VHDL parser. For more details on how to use this tool, see the capsule
$VOVDIR/eda/Synopsys/vov_vhdlan.tcl
Capsules for Verilog Tools
A package of procedures to deal with Verilog-based tools is found in $VOVDIR/eda/Verilog/vovverilog.tcl.
In particular:
vv_find_libraries
helps parse the vsystem.ini filesvv_find_modules finds
all module definitionsvv_do_instances
processes all instances
A generic capsule for a verilog simulator is $VOVDIR/eda/Verilog/vov_generic_verilog.tcl.
For example, if you need the capsule for the Verilog simulator silos by Simucad, you
can get it by creating a link with the generic verilog capsule, as in:
% cd $VOVDIR/eda/Verilog
% ln -s vov_generic_verilog.tcl vov_silos.tcl